1. Field of the Invention
The present invention is generally in the field of semiconductors. More specifically, the present invention is in the field of fabrication of semiconductor transistors.
2. Background Art
Complementary metal-oxide-semiconductor (CMOS) technology is widely utilized in the semiconductor industry due to its numerous advantages. For example, the high density, low power consumption, and relative noise immunity associated with CMOS devices make them desirable for implementation in integrated circuits (ICs), to provide control logic for modem electronic systems, for instance. However, standard CMOS transistors are typically low voltage devices. As a result, power applications, such as power switching and voltage regulation, for example, are typically performed by high power versions of metal-oxide-semiconductor field-effect transistors (MOSFETs), such as lateral diffused metal-oxide-semiconductor (LDMOS) devices, often fabricated alongside the CMOS logic devices on the IC die.
Not surprisingly, one important measure of LDMOS device performance is its breakdown voltage, which should preferably be high. Yet another important measure of LDMOS performance is its ON-resistance, or Rdson, which should preferably be quite low. As device dimensions continue to be reduced, so called short-channel effects, such as channel leakage, can result in undesirable power loss even when a transistor is nominally OFF. In an attempt to reduce or substantially eliminate OFF-state leakage in standard CMOS transistors, CMOS fabrication is increasingly moving to fin-based field-effect transistor (FinFET) architectures, due in part to the improved channel depletion achievable using FinFET designs. However, adoption of the FinFET architecture renders implementation of an LDMOS having a desirably low Rdson significantly more challenging.
Strategies for lowering Rdson in conventional LDMOS device structures may include manipulating the proximity of the transistor gate and various drain side features. For example, the Rdson of a conventional LDMOS device can be lowered by reducing the width of a shallow trench isolation (STI) structure formed between the gate and the highly doped drain region, or by increasing the overlap of the gate over the drain extension well surrounding the STI structure. However, those conventional modifications of the LDMOS device undertaken to advantageously reduce Rdson may concurrently and undesirably result in a reduced breakdown voltage for the LDMOS device.
Thus, there is a need to overcome the drawbacks and deficiencies in the art by providing a solution compatible with emerging CMOS process flows, capable of producing a power MOSFET configured to concurrently exhibit low Rdson and robust resistance to voltage breakdown.